Renesas SH7781 - Manual (Page 678)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 648 of 1658
REJ09B0261-0100
13.4.5 Host Mode
(1) Operation in Host Mode
The PCI interface of this LSI supports a subset of the PCI version 2.2 and can be connected to a
device with a PCI bus interface.
According to the PCIC mode, host mode or normal mode, operation differs in two points: (1) the
PCIC unconditionally performs bus parking or not, and (2) the PCI bus arbitration function is
enabled or disabled.
In host mode, the PCIC drives the AD, C/
BE, PAR signal lines when a transfer is not performed
on the PCI bus. When the PCIC subsequently starts a transfer as the master, the PCIC continues to
drive these signal lines until the address phase ends.
The REQ and GNT signals between PCIC and an arbiter in the PCIC are internally connected.
Here, pins
REQ0/REQOUT, REQ1, REQ2, and REQ3 function as the REQ inputs from external
masters 0 to 3. Similarly,
GNT0/GNTIN, GNT1, GNT2, and GNT3 function as the GNT outputs
to external masters 0 to 3. Arbitration for five masters including the PCIC can be performed.
(2) Configuration Space Access
The PCIC supports configuration mechanism #1. The PCI PIO address register (PCIPAR) and PCI
PIO data register (PCIPDR) correspond to the configuration address register and configuration
data register, respectively.
When PCIPAR is set and PCIPDR is read or written to, a configuration cycle is issued on the PCI
bus. For the type-0 transfer, bits 10 to 2 of the configuration address register are sent to the PCI
bus without translation and AD31 to AD11 are changed to be used as the IDSEL signal.
When the device number is set to 0, AD16 is driven to 1 and the other bits are made to be 0.
When the device number is set to 1, AD17 is driven to 1 and the other bits are made to be 0.
Similarly, setting the device number to 2 drives AD18 to 1 and setting the device number to 3
drives AD19 to 0.
When the device number is set to 16, AD31 is driven to 1 and the other bits are made to be 0.