Figure 4.2 instruction execution patterns (8) – Renesas SH7781 User Manual
Page 104
4. Pipelining
Rev.1.00 Jan. 10, 2008 Page 74 of 1658
REJ09B0261-0100
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(6-12) Single-precision FABS, FNEG/double-precision FABS, FNEG: 1 issue cycle
(6-13) FLDI0, FLDI1: 1 issue cycle
(6-14) Single-precision floating-point computation: 1 issue cycle
(6-15) Single-precision FDIV/FSQRT: 1 issue cycle
(6-16) Double-precision floating-point computation: 1 issue cycle
(6-17) Double-precision floating-point computation: 1 issue cycle
(6-18) Double-precision FDIV/FSQRT: 1 issue cycle
FEDS (Divider occupied cycle)
FCMP/EQ, FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRCHG, FSCHG, FPCHG
FCMP/EQ, FCMP/GT, FADD, FLOAT, FSUB, FTRC, FCNVSD, FCNVDS
FMUL
FEDS (Divider occupied cycle)
Figure 4.2 Instruction Execution Patterns (8)