11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 443 of 1658
REJ09B0261-0100
T1
T2
CLKOUT
A25 to A0
CSn
R/
W
RD
D31 to D0
(In reading)
BS
DACKn
RDY
WEn
In this example, DACKn is active-high.
Figure 11.38 Basic Read Cycle of Byte Control SRAM (No Wait)