Renesas SH7781 - Manual (Page 145)

5. Exception Handling
Rev.1.00 Jan. 10, 2008 Page 115 of 1658
REJ09B0261-0100
(10) Slot Illegal Instruction Exception
• Sources:
⎯ Decoding of an undefined instruction in a delay slot
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Undefined instruction: H'FFFD
⎯ Decoding of an instruction that modifies PC in a delay slot
Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,
BT/S, BF/S, TRAPA, LDC Rm,SR, LDC.L @Rm+,SR, ICBI, PREFI
⎯ Decoding in user mode of a privileged instruction in a delay slot
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC
instructions that access GBR
⎯ Decoding of a PC-relative MOV instruction or MOVA instruction in a delay slot
⎯ The BRDSSLP bit in EXPMASK is 0, and the SLEEP instruction in the delay slot is
executed.
⎯ The RTEDS bit in EXPMASK is 0, and an instruction other than the NOP instruction in the
delay slot is executed.
• Transition address: VBR + H'000 0100
• Transition operations:
The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and
R15 contents when this exception occurred are saved in SSR and SGR.
Exception code H'1A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100. Operation is not guaranteed if an undefined code other
than H'FFFD is decoded.
Slot_illegal_instruction_exception()
{
SPC = PC - 2;
SSR = SR;
SGR = R15;
EXPEVT = H'0000 01A0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'0000 0100;
}