Renesas SH7781 - Manual (Page 75)

3. Instruction Set
Rev.1.00 Jan. 10, 2008 Page 45 of 1658
REJ09B0261-0100
Section 3 Instruction Set
This LSI's instruction set is implemented with 16-bit fixed-length instructions. This LSI can use
byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory
access. Single-precision floating-point data (32 bits) can be moved to and from memory using
longword or quadword size. Double-precision floating-point data (64 bits) can be moved to and
from memory using longword size. When this LSI moves byte-size or word-size data from
memory to a register, the data is sign-extended.
3.1 Execution Environment
(1)
PC
At the start of instruction execution, the PC indicates the address of the instruction itself.
(2) Load-Store Architecture
This LSI has a load-store architecture in which operations are basically executed using registers.
Except for bit-manipulation operations such as logical AND that are executed directly in memory,
operands in an operation that requires memory access are loaded into registers and the operation is
executed between the registers.
(3)
Delayed Branches
Except for the two branch instructions BF and BT, this LSI's branch instructions and RTE are
delayed branches. In a delayed branch, the instruction following the branch is executed before the
branch destination instruction.
(4) Delay Slot
This execution slot following a delayed branch is called a delay slot. For example, the BRA
execution sequence is as follows: