Renesas SH7781 - Manual (Page 836)

18. Timer Unit (TMU)
Rev.1.00 Jan. 10, 2008 Page 806 of 1658
REJ09B0261-0100
18.3.2 Timer Constant Registers (TCORn) (n = 0 to 5)
The TCOR registers are 32-bit readable/writable registers. When a TCNT counter underflows
while counting down, the TCOR value is set in that TCNT, which continues counting down from
the set value.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 BIt:
Initial value:
R/W:
18.3.3 Timer Counters (TCNTn) (n = 0 to 5)
The TCNT registers are 32-bit readable/writable registers. Each TCNT counts down on the input
clock selected by the TPSC2 to TPSC0 bits in TCR.
When a TCNT counter underflows while counting down, the UNF flag is set in TCR of the
corresponding channel. At the same time, the TCOR value is set in TCNT, and the count-down
operation continues from the set value.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 BIt:
Initial value:
R/W: