Renesas SH7781 User Manual
Page 951
19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 921 of 1658
REJ09B0261-0100
19.3.52
External Synchronization Control Register (ESCR)
The external synchronization control register (ESCR) controls the dot clock.
R/W:
Internal update:
R/W:
Internal update:
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
Bit:
Initial value:
R/W
R
R
R
R/W
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DCLK
DIS
—
—
—
DCLK
SEL
—
—
—
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FRQSEL
—
—
—
—
—
—
—
—
—
—
—
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
Bit:
Initial value:
Bit Bit
Name
Initial
Value R/W
Internal
Update Description
31 to 21
⎯ All
0
R
⎯ Reserved
These bits are always read as 0. The write value
should always be 0.
20
DCLKSEL
0 R/W
None
DOTCLKIN
Select
To enable this bit, the DCKE bit in DEFR should
be set to 1. In the initial state, this bit is fixed to 0.
0: The input dot clock source is the DCLKIN pin
1: The input dot clock is DUck
This setting should be made such that the
frequency of the frequency-divided dot clock
generated by the dot clock generation circuit is
50 MHz or lower.
19 to 17
⎯ All
0
R
⎯ Reserved
These bits are always read as 0. The write value
should always be 0.
16 DCLKDIS 0
R/W
None
DOTCLKOUT
Disable
0: DOTCLKOUT is output.
1: DOTCLKOUT is not output.
DOTCLKOUT is fixed to low level.
15 to 5
⎯ All
0
R
⎯ Reserved
These bits are always read as 0. The write value
should always be 0.