Renesas SH7781 - Manual (Page 262)

8. Caches
Rev.1.00 Jan. 10, 2008 Page 232 of 1658
REJ09B0261-0100
8.6 Memory-Mapped Cache Configuration
The IC and OC can be managed by software. The contents of IC data array can be read from or
written to by a program in the P2 area by means of a MOV instruction in privileged mode. The
contents of IC address array can also be read from or written to in privileged mode by a program
in the P2 area or the IL memory area by means of a MOV instruction. Operation is not guaranteed
if access is made from a program in another area. In this case, execute one of the following three
methods for executing a branch to the P0, U0, P1, or P3 area.
1. Execute a branch using the RTE instruction.
2. Execute a branch to the P0, U0, P1, or P3 area after executing the ICBI instruction for any
address (including non-cacheable area).
3. If the MC bit in IRMCR is 0 (initial value) before making an access to the memory-mapped
IC, the specific instruction does not need to be executed. However, note that the CPU
processing performance will be lowered because the instruction fetch is performed again for
the next instruction after making an access to the memory-mapped IC.
Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is
recommended that the method 1 or 2 should be used for being compatible with the future SuperH
Series.
In privileged mode, the OC contents can be read from or written to by a program in the P1 or P2
area by means of a MOV instruction. Operation is not guaranteed if access is made from a
program in another area. The IC and OC are allocated to the P4 area in the virtual address space.
Only data accesses can be used on both the IC address array and data array and the OC address
array and data array, and accesses are always longword-size. Instruction fetches cannot be
performed in these areas. For reserved bits, a write value of 0 should be specified and the read
value is undefined.
8.6.1 IC Address Array
The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification. The way and entry to be accessed are specified in the address field,
and the write tag and V bit are specified in the data field.
In the address field, bits [31:24] have the value H'F0 indicating the IC address array, and the way
is specified by bits [14:13] and the entry by bits [12:5]. The association bit (A bit) [3] in the
address field specifies whether or not association is performed when writing to the IC address
array. As only longword access is used, 0 should be specified for address field bits [1:0].