Renesas SH7781 - Manual (Page 171)

6. Floating-Point Unit (FPU)
Rev.1.00 Jan. 10, 2008 Page 141 of 1658
REJ09B0261-0100
(2) FTRV XMTRX, FVn (n: 0, 4, 8, 12)
This instruction is basically used for the following purposes:
• Matrix (4 × 4) ⋅ vector (4):
This operation is generally used for viewpoint changes, angle changes, or movements called
vector transformations (4-dimensional). Since affine transformation processing for angle +
parallel movement basically requires a 4
× 4 matrix, this LSI supports 4-dimensional
operations.
• Matrix (4 Ч 4) Ч matrix (4 × 4):
This operation requires the execution of four FTRV instructions.
Since an inexact exception is not detected by an FIRV instruction, the inexact exception (I) bit in
both the FPU exception cause field and flag field are always set to 1 when an FTRV instruction is
executed. Therefore, if the I bit is set in the FPU exception enable field, FPU exception handling
will be executed. It is not possible to check all data types in the registers beforehand when
executing an FTRV instruction. If the V bit is set in the FPU exception enable field, FPU
exception handling will be executed.
(3) FRCHG
This instruction modifies banked registers. For example, when the FTRV instruction is executed,
matrix elements must be set in an array in the background bank. However, to create the actual
elements of a translation matrix, it is easier to use registers in the foreground bank. When the LDS
instruction is used on FPSCR, this instruction takes four to five cycles in order to maintain the
FPU state. With the FRCHG instruction, the FR bit in FPSCR can be changed in one cycle.
6.6.2 Pair Single-Precision Data Transfer
In addition to the powerful new geometric operation instructions, this LSI also supports high-
speed data transfer instructions.
When the SZ bit is 1, this LSI can perform data transfer by means of pair single-precision data
transfer instructions.
• FMOV DRm/XDm, DRn/XDRn (m, n: 0, 2, 4, 6, 8, 10, 12, 14)
• FMOV DRm/XDm, @Rn (m: 0, 2, 4, 6, 8, 10, 12, 14; n: 0 to 15)
These instructions enable two single-precision (2
× 32-bit) data items to be transferred; that is, the
transfer performance of these instructions is doubled.
• FSCHG