Renesas SH7781 User Manual
Page 1302
25. Audio Codec Interface (HAC)
Rev.1.00 Jan. 10, 2008 Page 1272 of 1658
REJ09B0261-0100
Bit Bit
Name
Initial
Value R/W Description
18
17
16
15
14
13
12
CA6/SA6
CA5/SA5
CA4/SA4
CA3/SA3
CA2/SA2
CA1/SA1
CA0/SA0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Codec Control Register Addresses 6 to 0/Codec Status
Register Addresses 6 to 0
[Write]
Specify the address of the codec register to be written.
[Read]
Indicate the status address received via slot 1,
corresponding to the codec register whose data has
been returned in HACCSDR.
11
10
9
8
7
6
5
4
3
2
SLREQ3
SLREQ4
SLREQ5
SLREQ6
SLREQ7
SLREQ8
SLREQ9
SLREQ10
SLREQ11
SLREQ12
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
Slot Requests 3 to 12
Valid only in the RX frame. Indicate whether the codec
is requesting slot data in the next TX frame.
Automatically set by hardware, and correspond to bits
11 to 2 of slot 1 in the RX frame.
0: Slot data is requested.
1: Slot data is not requested.
1, 0
⎯ All
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.