Renesas SH7781 - Manual (Page 722)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 692 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Descriptions
0 DME 0 R/W DMA Master Enable
Enables or disables DMA transfers on all channels
(channels 0 to 5) corresponding to DMAOR0, and all
channels (channels 6 to 11) corresponding to
DMAOR1. If the DME bit, and the DE bit in CHCR are
set to 1, transfer is enabled. All of the TE bit in CHCR in
the channel that executes transfer, NMIF, and AE in
DMAOR corresponding to channels should be 0. If the
DME bit is cleared to 0, transfers in all channels
(channels 0 to 5) corresponding to DMAOR0 and all
channels (channels 6 to 11) corresponding to DMAOR1
are aborted.
In an on-chip peripheral module request, when aborting
the transfer by clearing the DME bit, clear the DME bit
while all on-chip peripheral module transfer requests
corresponding channels of DMAOR is cleared.
0: DMA transfers on channels 0 to 5 disabled
(DMAOR0)
DMA transfers on channels 6 to 11 disabled
(DMAOR1)
1: DMA transfers on channels 0 to 5 enabled
(DMAOR0)
DMA transfers on channels 6 to 11 enabled
(DMAOR1)
Note: * To clear the flag, 0 can be written to.