7 dmac module signal timing, 0 to 3.6 v, v, 5 v, t – Renesas SH7781 User Manual
Page 1631: 40 to 85°c, c, 30 pf, pll2 on, Figure 32.40 dreq / drak signal timing
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32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1601 of 1658
REJ09B0261-0100
t
PCISU
0.4V
DDQ
PCICLK
Input
0.4V
DDQ
t
PCIH
Figure 32.39 PCI Input Signal Timing
32.3.7
DMAC Module Signal Timing
Table 32.12 DMAC Module Signal Timing
Conditions: V
DDQ
= 3.0 to 3.6 V, V
DD
= 1.5 V, T
a
=
−40 to 85°C, C
L
= 30 pF, PLL2 on
Module Item
Symbol Min.
Max. Unit Figure
Remarks
DMAC
DREQ setup time
t
DRQS
2.5 — ns
32.40
DREQ hold time
t
DRQH
1.5 —
DRAK delay time
t
DRAKD
1.5 6
DACK delay time
t
DAKD
1.5 6
t
DRQS
CLKOUT
DRAK
DREQ
t
DRQH
t
DRAKD
t
DRAKD
Figure 32.40
DREQ/DRAK Signal Timing
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