15 hac interface module signal timing, Figure 32.58 hac cold reset timing – Renesas SH7781 User Manual
Page 1644
32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1614 of 1658
REJ09B0261-0100
t
MMRCS
t
MMRCH
MMCCLK
MMCCMD (Input)
MMCDAT (Input)
t
MMRDS
t
MMRDH
Figure 32.57 MMCIF Reception Timing (Sampling on Rising Edges)
32.3.15
HAC Interface Module Signal Timing
Table 32.20 HAC Interface Module Signal Timing
Item Symbol
Min.
Max.
Unit
Figure
HAC_RES active low pulse width
t
RST_LOW
1000
—
ns 32.58
HAC_SYNC active pulse width
t
SYN_HIGH
1000
—
ns 32.59
HAC_SYNC delay time 1
t
SYNCD1
—
15
ns
HAC_SYNC delay time 2
t
SYNCD2
—
15
ns
HAC_SDOUT delay time
t
SDOUTD
—
15
ns
HAC_SDIN setup time
t
SDIN0S
10
— ns
HAC_SDIN hold time
t
SDIN0H
10
— ns
32.61
HAC_BITCLK input high level width
t
ICL0_HIGH
t
Pcyc
/2 — ns
32.60
HAC_BITCLK input low level width
t
ICL0_LOW
t
Pcyc
/2 — ns
Note: t
Pcyc
is the period of one peripheral clock (Pck) cycle.
HAC_RES
t
RST_LOW
Figure 32.58 HAC Cold Reset Timing