Renesas SH7781 - Manual (Page 1022)

20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 992 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
1 CL_OA 0 R/W Specifies output address mode
0: Output address incremented
When the output access size is 4 bytes, the address is
incremented by H'4; when the output access size is 32
bytes, the address is incremented by H'20.
1: Output address fixed
The address set in CLCF as command parameter 4
(output pointer) is output.
0 CL_MD 0 R/W Specifies conversion mode
0: YUYV conversion
Converts from YUV420 to YUV422 format
1: ARGB conversion
Converts from YUV420 to ARGB8888 format
A Table of CL_DA Register Settings And Output Data Alignment
CL_DA
YUYV
Conversion ARGB
Conversion CL_DA YUYV
Conversion ARGB
Conversion
H'0 Y0UY1V ARGB H'10 UVY0Y1 RBAG
H'1 Y0UVY1 ARBG H'11 UVY1Y0 RBGA
H'2 Y0Y1UV AGRB H'12 VY1Y0U BGAR
H'3 Y0Y1VU AGBR H'13 VY1UY0 BGRA
H'4 Y0VY1U ABGR H'14 VY0Y1U BAGR
H'5 Y0VUY1 ABRG H'15 VY0UY1 BARG
H'6 Y1UY0V GRAB H'16 VUY0Y1 BRAG
H'7 Y1UVY0 GRBA H'17 VUY1Y0 BRGA
H'8 Y1Y0UV GARB H'18 Y0UY1V ARGB
H'9 Y1Y0VU GABR H'19 Y0UY1V ARGB
H'A Y1VY0U GBAR H'1A Y0UY1V ARGB
H'B Y1VUY0 GBRA H'1B Y0UY1V ARGB
H'C UY1Y0V RGAB H'1C Y0UY1V ARGB
H'D UY1VY0 RGBA H'1D Y0UY1V ARGB
H'E UY0Y1V RAGB H'1E Y0UY1V ARGB
H'F UY0VY1 RABG H'1F Y0UY1V ARGB