Renesas SH7781 - Manual (Page 463)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 433 of 1658
REJ09B0261-0100
Tm1
CLKOUT
RD/FRAME
CSn
R/ W
D63 to D0
BS
Tmd1w Tmd1 Tmd2 Tmd3 Tmd4
RDY
DACKn
D1 D2 D3 D0 A
In this example, DACKn is active-high.
Figure 11.28 MPX Interface Timing 5
(Burst Read Cycle, IW
= 0000, No External Wait, 64-Bit Bus Width, 32-Byte Data Transfer)