Renesas SH7781 - Manual (Page 754)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 724 of 1658
REJ09B0261-0100
Bus cycle
DREQ
(Overrun 0, High level)
DRAK (High-active)
DACK (High-active)
Bus cycle
DREQ
(Overrun 1, High level)
DRAK (High-active)
DACK (High-active)
: Non-sensitive period
CLKOUT
Acceptance started
Accepted after one cycle of CLKOUT
at the first falling edge of the divided-up DACK
1st acceptance 2nd acceptance
CPU CPU DMAC
: Non-sensitive period
CLKOUT
Acceptance started
Accepted after one cycle of CLKOUT
at the first rising edge of the divided-up DACK
1st acceptance 2nd acceptance
CPU CPU DMAC
Figure 14.17 Example 2 of DREQ Input Detection in Cycle Steal Mode Level Detection
(Word Transfer in 8-Bit Bus Width, Longword Transfer in 8/16-Bit Bus Width, 16/32-Byte
Transfer in 8/16/32/64-Bit Bus Width: DACK of DMA1 Transfer Divided)