Renesas SH7781 - Manual (Page 728)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 698 of 1658
REJ09B0261-0100
• DMARS4
Bit Bit Name
Initial
Value R/W Descriptions
15
14
13
12
11
10
C9MID5
C9MID4
C9MID3
C9MID2
C9MID1
C9MID0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Transfer request source module ID5 to ID0 for DMA
channel 9 (MID)
See table 14.3.
9
8
C9RID1
C9RID0
0
0
R/W
R/W
Transfer request source register ID1 and ID0 for DMA
channel 9 (RID)
See table 14.3.
7
6
5
4
3
2
C8MID5
C8MID4
C8MID3
C8MID2
C8MID1
C8MID0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Transfer request source module ID5 to ID0 for DMA
channel 8 (MID)
See table 14.3.
1
0
C8RID1
C8RID0
0
0
R/W
R/W
Transfer request source register ID1 and ID0 for DMA
channel 8 (RID)
See table 14.3.