Renesas SH7781 - Manual (Page 413)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 383 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
27
⎯ 0
R Reserved
This bit is always read as 0. The write value should
always be 0.
26 to 24 SAB 111 R/W Space Property B
These bits specify the space property of PCMCIA
connected to the second half of the area.
000: ATA complement mode
001: Dynamic I/O bus sizing
010: 8-bit I/O space
011: 16-bit I/O space
100: 8-bit common memory
101: 16-bit common memory
110: 8-bit attribute memory
111: 16-bit attribute memory
23, 22 PCWA 00 R/W PCMCIA Wait A
These bits specify the number of wait cycles for low-
speed PCMCIA, which is added to the number set by
the IW bits in CSnWCR.
The bit settings are selected when the access area of
PCMCIA interface is the first half.
00: No wait cycle inserted
01: 15 wait cycles inserted
10: 30 wait cycles inserted
11: 50 wait cycles inserted
21, 20 PCWB 00 R/W PCMCIA Wait B
These bits specify the number of wait cycles for low-
speed PCMCIA, which is added to the number set by
the PCIW bits.
The bit settings are selected when the access area of
PCMCIA interface is the second half.
00: No wait cycle inserted
01: 15 wait cycles inserted
10: 30 wait cycles inserted
11: 50 wait cycles inserted