Renesas SH7781 - Manual (Page 212)

7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 182 of 1658
REJ09B0261-0100
7.6 MMU Exceptions
There are seven MMU exceptions: instruction TLB multiple hit exception, instruction TLB miss
exception, instruction TLB protection violation exception, data TLB multiple hit exception, data
TLB miss exception, data TLB protection violation exception, and initial page write exception.
Refer to figures 7.9, 7.10, 7.14, 7.15, and section 5, Exception Handling for the conditions under
which each of these exceptions occurs.
7.6.1 Instruction TLB Multiple Hit Exception
An instruction TLB multiple hit exception occurs when more than one ITLB entry matches the
virtual address to which an instruction access has been made. If multiple hits occur when the
UTLB is searched by hardware in hardware ITLB miss handling, an instruction TLB multiple hit
exception will result.
When an instruction TLB multiple hit exception occurs, a reset is executed and cache coherency is
not guaranteed.
(1) Hardware Processing
In the event of an instruction TLB multiple hit exception, hardware carries out the following
processing:
1. Sets the virtual address at which the exception occurred in TEA.
2. Sets exception code H'140 in EXPEVT.
3. Branches to the reset handling routine (H'A000 0000).
(2) Software Processing (Reset Routine)
The ITLB entries which caused the multiple hit exception are checked in the reset handling
routine. This exception is intended for use in program debugging, and should not normally be
generated.