Renesas SH7781 - Manual (Page 517)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 487 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
15 to 10
⎯
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
9, 8 BASFT1
and
BASFT0 00 R/W Bank Address Shift Bits
These bits select the amount of shifting downward of
the bank address.
00: No shift
01: Shift the bank address downward 1 bit.
10: Shift the bank address downward 2 bits.
11: Shift the bank address downward 3 bits.
7 to 3
⎯
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
1, 0 BWIDTH1
and
BWIDTH0 01 R/W SDRAM Bus Width Setting Bits
These bits set the external data bus width.
00: Setting prohibited (If specified, correct operation
cannot be guaranteed.)
01: 16 bits
10: 32 bits
11: Setting prohibited (If specified, correct operation
cannot be guaranteed.)
Note: Writing to this register should be performed only when the following conditions are met.
• When SDRAM access is disabled (when the ACEN bit in the DBEN register is 0.).
• When automatic issue of auto-refresh is disabled (when the ARFEN bit in the
DBRFCNT0 register is cleared to 0.).