Renesas SH7781 - Manual (Page 509)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 479 of 1658
REJ09B0261-0100
12.4 Register Descriptions
Table 12.9 shows the DBSC2 register configuration; Table 12.10 shows register states in the
different processing modes.
The register bit width is 32 bits, and the longword size (32 bits) should be used for register access.
If registers are accessed with sizes other than the longword size, correct operation cannot be
guaranteed.
The DBSC2 register area is, in P4 addresses, from H'FE80 0000 to H'FEFF FFFF and in area 7
addresses, from H'FE800000 to H'FEFFFFFA. If an address other than the register addresses
indicated in table 12.9 is accessed, correct operation cannot be guaranteed.