Renesas SH7781 - Manual (Page 1519)

30. User Debugging Interface (H-UDI)
Rev.1.00 Jan. 10, 2008 Page 1489 of 1658
REJ09B0261-0100
30.2 Input/Output Pins
Table 30.1 shows the pin configuration of the H-UDI.
Table 30.1 Pin Configuration of H-UDI
Pin Name Function I/O Description
When Not
in Use
TCK Clock Input The functions are the same as the serial clock
input pin of JTAG. In synchronization with this
signal, data is sent from the TDI pin to the H-
UDI circuit or data is read from the TDO pin. Open* 1
TMS Mode Input Mode Select Input Pin
The meaning of data input from the TDI pin is
determined by changing this signal in
synchronization with TCK. The protocol
supports JTAG (IEEE 1149.1) with the subset.
Open* 1
TRST* 2 Reset Input H-UDI Reset Input Pin
This signal is received without relating to TCK.
The JTAG interface circuit is reset when this
signal is at a low level. Regardless of whether
JTAG is used or not,
TRST should be set to a
low level during a specific period when power is
turned on. This does not conform to the IEEE
standard.
Fixed to
ground or
connected to
the
PRESET
pin* 3
TDI Data input Input Data Input Pin
Data is sent to the H-UDI circuit by changing
this signal in synchronization with TCK.
Open* 1
TDO Data output Output Data Output Pin
Data is read from the H-UDI circuit by reading
this signal in synchronization with TCK.
Open
ASEBRK/
BRKACK
Emulator I/O Pins for emulators Open* 1
AUDSYNC,
AUDCK,
AUDATA3 to
AUDATA0 Emulator Output Pins for emulators Open
MPMD Chip-mode Input Indicates whether the operating mode of this
LSI is emulation support mode (MPMD = 0) or
chip mode (MPMD = 1). Open