Renesas SH7781 - Manual (Page 682)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 652 of 1658
REJ09B0261-0100
D0
(Nomal state)
D2
(Clock stopped)
D1
(Bus idle)
D3
(Power-down)
Figure 13.18 Power Down State Transitions on PCI Bus
When the PCIC detects that the power state (PS) bit in PCIPMCSR changes (PS is written by an
external PCI device), it issues a power management interrupt. PCIPINT and PCIPINTM are used
to control the power management interrupts. As the power management interrupts, PCIPWD0 that
detects a transition from the power state D1/D2/D3 to D0, PCIPWD1 that detects a transition from
the power state D0 to D1, PCIPWD2 that detects a transition from the power state D0/D1 to D2,
and PCIPWD3 that detects a transition from the power state D0/D1/D2 to D3 are supported. An
interrupt mask can be set for each interrupt.
The power state D0 interrupt is not generated at a power-on reset.
When the PCIC operates in normal mode and accepts a power down interrupt from an external
host device, note the following:
With the PCI power management function, the PCI bus clock is stopped 16 clocks or more after
the host device directs a transition to the power state D3. Therefore, after detecting a power state
D3 interrupt, do not attempt to read or write to the PCIC internal local registers and configuration
registers that can be accessed both from the CPU and PCI bus, and PCI local bus accesses (I/O and
memory spaces). If the PCI bus clock stops during the access, the read/write cycle will not be
completed and hung up on the SuperHyway bus because these accesses operate with the PCI bus
clock