Renesas SH7781 - Manual (Page 1181)

23. Serial Peripheral Interface (HSPI)
Rev.1.00 Jan. 10, 2008 Page 1151 of 1658
REJ09B0261-0100
Section 23 Serial Peripheral Interface (HSPI)
This LSI incorporates one channel of the Serial Protocol Interface (HSPI).
23.1 Features
The HSPI has the following features.
• Operating mode: Master mode or Slave mode.
• The transmit and receive sections within the module are double buffered to allow duplex
communication.
• A flexible peripheral clock (Pck) division strategy allows a wide range of bit rates to be
supported.
• The programmable clock control logic allows setting for two different transmit protocols and
accommodates transmit and receive functions on either edge of the serial clock.
• Error detection logic is provided for warning of the receive buffer overflow.
• The HSPI has a facility to generate the chip select signal to slave modules when configured as
a master either automatically as part of the data transfer process, or under the manual control
of the host processor.
• Both the transmit data and receive data can be DMA transferred independently via the two
DMA channels.