Renesas SH7781 - Manual (Page 571)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 541 of 1658
REJ09B0261-0100
MCK0,
MCK1
MA[14:11]
MA[9:0]
MBA[2:0]
MCKE
MCS
MRAS
MCAS
MWE
MA[10]
WRITE
any
bank
Invalid
MDQS[3:0]
MDQ[31:0]
MDM[3:0] Invalid
Invalid Invalid
Invalid
Invalid
READ
any
bank
Invalid
Invalid
Invalid
SDRAM
command
Invalid
Invalid
Write data Read data
Valid
Valid
Valid
Valid
Valid
Valid
Example of CL = 3
RDWR
= 4 cycles
High level
Figure 12.18 READ-WRITE Minimum Time
Figure 12.18 is an example of a case in which, after issuing a READ command, a WRITE
command is issued. In order to issue the WRITE command after issuing the READ command, the
DBSC2 waits for a minimum time stipulated by the RDWR bits.