Renesas SH7781 - Manual (Page 464)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 434 of 1658
REJ09B0261-0100
Tm1
CLKOUT
A
RD/FRAME
CSn
R/ W
D63 to D0
BS
Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4
RDY
DACKn
D3 D1 D2 D0
In this example, DACKn is active-high.
Figure 11.29 MPX Interface Timing 6 (Burst Read Cycle, IW
= 0000,
External Wait Control, 64-Bit Bus Width, 32-Byte Data Transfer)