Renesas SH7781 User Manual
Page 705
14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 675 of 1658
REJ09B0261-0100
14.3.1
DMA Source Address Registers 0 to 11 (SAR0 to SAR11)
SAR are 32-bit readable/writable registers that specify the source address of a DMA transfer.
During a DMA transfer, these registers indicate the source address of the next transfer. A word or
longword boundary address should be specified when a word or longword transfer is performed
respectively. A 16-byte or 32-byte boundary value should be specified when a 16-byte or 32-byte
transfer is performed respectively.
In 29-bit address mode, the source address is changed as follows before it is output.
• The upper three bits are output as 000 when bits 31 to 29 are not 111 and areas 0 to 6 are used.
• The upper three bits are output as 111 when bits 31 to 29 are not 111 and area 7 is used.
• The written address is output as it is when bits 31 to 29 are 111.
In 32-bit address mode, the written address is output as it is.
The initial value of SAR is undefined.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BIt:
Initial value:
R/W:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BIt:
Initial value:
R/W: