Renesas SH7781 - Manual (Page 478)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 448 of 1658
REJ09B0261-0100
11.5.9 Bus Arbitration
This LSI is provided with a bus arbitration function that gives the bus to an external device when a
request is issued from the device.
This bus arbitration supports master mode and slave mode. In master mode the bus is held on a
steady state, and is released to another device in response to a bus request. In slave mode, the bus
is not held in the steady state. Each time the external bus cycle occurs, the bus mastership is
required, and the bus is released after completion of access.
Master mode and slave mode are specified by the external mode pin settings. In master mode and
slave mode, the bus enters the high-impedance state when not being held. In master mode, it is
possible to connect an external device that issues bus requests. In the following description, an
external device that issues bus requests is called a slave.
This LSI has five internal bus masters, the CPU, DMAC, GDTA, DU, and PCIC. In addition to
them, bus requests from external devices are issued. If requests occur simultaneously, priority is
given, in high-to-low order, to a bus request from an external device, and internal bus master. The
priority of the bus masters in this LSI is round-robin.
To prevent incorrect operation of connected devices when the bus is transferred between master
and slave, all bus control signals are negated before the bus is released. In addition, when the bus
mastership is received, bus control signals begin driving the bus from the negated state. Since the
same signals are driven by the master and slave that exchange the bus, output buffer collisions can
be avoided.
Bus transfer is executed between bus cycles.
When the bus release request signal (
BREQ) is asserted, this LSI releases the bus as soon as the
currently executing bus cycle ends, and outputs the bus use permission signal (
BACK). However,
bus release is not performed during multiple bus cycles generated because the data bus width is
smaller than the access size (for example, when performing longword access to 8-bit bus width
memory) or during a 32-byte transfer such as a cache fill or write-back. In addition, bus release is
not performed between read and write cycles during execution of a TAS instruction, or between
read and write cycles. When
BREQ is negated, BACK is negated and use of the bus is resumed.
Since the CPU in this LSI is connected to cache memory by a dedicated internal bus, reading from
cache memory can be carried out when the bus is being used by another bus master inside or
outside the LSI. In writing from the CPU, an external write cycle is generated when write-through
has been set for the cache in this LSI, or when an access is made to a cache-off area. In this case,
operation is waited until the bus is returned.