Renesas SH7781 - Manual (Page 526)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 496 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
20 to 16 TRC4 to
TRC0
0 0100 R/W tRC (ACT-ACT/REF period) Setting Bits
These bits set the constraint for the minimum time from
ACT command to ACT command (in the same bank)/
REF command. These bits should be set according to
the SDRAM specifications. The number of cycles is the
number of DDR clock cycles.
00000: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
:
00011: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
00100: 5 cycles
00101: 6 cycles
:
10010: 19 cycles
10011: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
:
11111: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
15 to 12
⎯
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.