8 dma operation register 0, 1 (dmaor0 and dmaor1) – Renesas SH7781 User Manual
Page 719
14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 689 of 1658
REJ09B0261-0100
14.3.8
DMA Operation Register 0, 1 (DMAOR0 and DMAOR1)
DMAOR are 16-bit readable/writable registers that specify the priority of channels in DMA
transfer. Also, these registers show the DMA transfer status.
DMAOR 0 is a register common to channels 0 to 5, and DMAOR1 is a register common to
channels 6 to11.
Note: * To clear the flag, 0 can be written to.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R/W
R/W
R
R
R/W
R/W
R
R
R
R
R
R/(W)*R/(W)* R/W
CMS[1:0]
PR[1:0] AE
NMIF DME
Bit:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W Descriptions
15, 14
⎯ All
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
13,
12 CMS[1:0]
00
R/W Cycle Steal Mode Select 1, 0
Select normal mode or intermittent mode in cycle steal
mode.
To validate intermittent mode, bus mode in all channels
(channels 0 to 5) corresponding to DMAOR0 or all
channels (channels 6 to 11) corresponding to DMAOR1
should be in cycle steal mode.
00: Normal mode
01: Setting prohibited
10: Intermittent mode 16
Executes a DMA transfer after waiting 16 Bck clock
of the external clock
11: Intermittent mode 64
Executes a DMA transfer after waiting 64 Bck clock
of the external clock
For details, see the descriptions on intermittent mode
16 and Intermittent mode 64, under section 14.4.3 (2)
(a), Cycle Steal Mode.