Renesas SH7781 - Manual (Page 592)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 562 of 1658
REJ09B0261-0100
13.3.1 PCIC Enable Control Register (PCIECR)
PCIECR is a register that specifies whether the PCIC is valid or invalid.
SH R/W:
PCI R/W:
SH R/W:
PCI R/W:
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit:
Initial value:
R R R R R R R R R R R R R R R R
— — — — — — — — — — — — — — — —
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
— — — — — — — — — — — — — — — —
R/W R R R R R R R R R R R R R R R
— — — — — — — — — — — — — — — —
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENBL — — — — — — — — — — — — — — —
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit:
Initial value:
Bit Bit Name
Initial
Value R/W Description
31 to 1 — All 0 SH: R
PCI:
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
0 ENBL 0 SH: R/W
PCI:
⎯
PCI Enable Bit.
Enables (validates) the PCIC. When this bit is 0, the
PCIC is disabled and the access from the CPU to the
PCIC, or from the external PCI device to the PCIC is
invalid (the PCIECR can be accessed). The access
from other CPU is invalid during writing and undefined
during reading. The access from the external PCI
device cannot be accepted).
0: PCIC disabled
1: PCIC enabled