Renesas SH7781 - Manual (Page 1091)

21. Serial Communication Interface with FIFO (SCIF)
Rev.1.00 Jan. 10, 2008 Page 1061 of 1658
REJ09B0261-0100
21.3.8 Bit Rate Register n (SCBRR)
SCBRR is an 8-bit register that sets the serial transmission/reception bit rate in accordance with
the baud rate generator operating clock selected by the CKS1 and CKS0 bits in SCSMR.
SCBRR can always be read from and written to by the CPU.
The SCBRR setting is found from the following equation.
Asynchronous mode:
N =
× 10 6 - 1
Pck
64
× 2 2n - 1 × B
Clocked synchronous mode:
N =
× 10 6 - 1
Pck
8 × 2 2n - 1 × B
Where B: Bit rate (bit/s)
N: SCBRR setting for baud rate generator (0
≤ N ≤ 255)
Pck: Peripheral module operating frequency (MHz)
n: 0, 1, 2, 3
(See table 21.3 for the relation between n and the baud rate generator input clock.)
Table 21.3 SCSMR Settings
SCSMR Setting
n Baud Rate Generator Input Clock CKS1 CKS0
0 Pck 0 0
1 Pck/4 0 1
2 Pck/16 1 0
3 Pck/64 1 1
The bit rate error in asynchronous mode is found from the following equation:
Error (%) = - 1 × 100
Pck × 10 6
(N + 1) × B Ч 64 Ч 2 2n - 1