Renesas SH7781 User Manual
Page 386
11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 356 of 1658
REJ09B0261-0100
Area
External
addresses Size
Connectable
Memory
Specifiable Bus
Width (bits)
Access Size*
7
SRAM
8, 16, 32, 64*
2
MPX 32,
64*
2
Burst ROM
8, 16, 32, 64*
2
6
H'1800 0000 to
H'1BFF FFFF
64 Mbytes
PCMCIA 8,
16*
2, 5
8/16/32 bits,
32 bytes
7*
7
H'1C00
0000
to
H'1FFF FFFF
64 Mbytes
⎯
⎯ —
Notes: 1. The memory bus width is specified by the external pins.
2. The memory bus width is specified by the register.
3. These areas can be allocated to DDR2-SDRAM by setting MMSELR. For details, see
section 12, DDR2-SDRAM Interface (DBSC2).
4. This area can be allocated to PCI memory by setting MMSELR. For details, see section
13, PCI Controller (PCIC).
5. When the PCMCIA interface is used, the bus width should be 8 or 16 bits.
6. Do not access the reserved area. If the reserved area is accessed, correct operation is
not be guaranteed.
7. If the LBSC is requested to perform 8- or 16-byte access by the bus master, the LBSC
performs accesses two or four times respectively with 32-bit access size.
Area 0:
H'0000 0000
Area 1:
H'0400 0000
Area 2:
H'0800 0000
Area 3:
H'0C00 0000
Area 4:
H'1000 0000
Area 5: (1st half) H'1400 0000
(2nd half) H'1600 0000
Area 6: (1st half) H'1800 0000
(2nd half) H'1A00 0000
SRAM/Burst ROM/MPX
SRAM/Burst ROM/MPX/Byte control SRAM
SRAM/Burst ROM/MPX
(DDR2-SDRAM)
SRAM/Burst ROM/MPX
(DDR2-SDRAM)
SRAM/Burst ROM/MPX/ Byte control SRAM
(DDR2-SDRAM/PCI)
SRAM/Burst ROM/MPX/PCMCIA *
(DDR2-SDRAM)
SRAM/Burst ROM/MPX/PCMCIA *
The PCMCIA interface is
also used for memory I/O
cards.
Note: * Any of these memory devices can be connected to each of the 1st and 2nd halves of the area.
Figure 11.3 Local Bus Memory Space Allocation