Renesas SH7781 - Manual (Page 670)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 640 of 1658
REJ09B0261-0100
13.4.4 Target Access
This section describes how the PCIC in this LSI is accessed by an external PCI local bus master
when the PCIC is used in both the host mode and normal mode.
(1)
Accessing Memory Space in This LSI
Accesses to the PCIC in this LSI by an external PCI bus master are described below.
I/O space
SHwy bus address space (4GB) PCI bus address space (4GB)
H'00000000
Local address
space 0 (base 0)
Memory base 1
I/O base
PCI I/O space
Memory base 0
H'FE000000
H'FE3FFFFF
H'FFFFFFFF
H '00000000
H'FFFFFFFF
Local address
space 1 (base 1)
Figure 13.10 Memory Map from PCI Bus to SuperHyway Bus