Renesas SH7781 - Manual (Page 747)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 717 of 1658
REJ09B0261-0100
14.4.4 DMA Transfer Flow
After intended transfer conditions are set to SAR, DAR, TCR, CHCR, DMAOR, and DMARS, the
DMAC transfers data according to the following procedure.
1. Checks if transfer is enabled (DE
= 1, DME = 1, TE = 0, AE = 0, NMIF = 0)
2. When a transfer request occurs while transfer is enabled, the DMAC transfers one transfer unit
of data (depending on the settings of TS0, TS1, and TS2). In auto-request mode, the transfer
starts automatically when the DE and DME bits are set to 1. The TCR is decremented for each
transfer. The actual transfer flows depend on address mode and bus mode.
3. When the specified number of transfers has been completed (when TCR is 0), the transfer ends
successfully. If the IE bit in CHCR is set to 1 at this time, a DMINT interrupt is sent to the
CPU.
4. When an address error or an NMI interrupt is generated by the DMAC, the transfer is aborted.
Transfers are also aborted when the DE bit in CHCR or the DME bit in DMAOR is cleared to
0.
Figure 14.11 shows a flowchart of DMA transfer.