Renesas SH7781 - Manual (Page 325)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 295 of 1658
REJ09B0261-0100
Bit Name
Initial
Value R/W Description
11 IC111 0 R/W Clears masking of the
interrupt source of
IRL7 to
IRL4 = LHLL (H'4).
10 IC110 0 R/W Clears masking of the
interrupt source of
IRL7 to
IRL4 = LHLH (H'5).
9 IC109 0 R/W Clears masking of the
interrupt source of
IRL7 to
IRL4 = LHHL (H'6).
8 IC108 0 R/W Clears masking of the
interrupt source of
IRL7 to
IRL4 = LHHH (H'7).
7 IC107 0 R/W Clears masking of the
interrupt source of
IRL7 to
IRL4 = HLLL (H'8).
[When read]
Undefined values are
read.
[When written]
0: No effect
1: Clears the
corresponding interrupt
mask (enables the
Interrupt)
6 IC106 0 R/W Clears masking of the
interrupt source of
IRL7 to
IRL4 = HLLH (H'9).
5 IC105 0 R/W Clears masking of the
interrupt source of
IRL7 to
IRL4 = HLHL (H'A).
4 IC104 0 R/W Clears masking of the
interrupt source of
IRL7 to
IRL4 = HLHH (H'B).
3 IC103 0 R/W Clears masking of the
interrupt source of
IRL7 to
IRL4 = HHLL (H'C).
2 IC102 0 R/W Clears masking of the
interrupt source of
IRL7 to
IRL4 = HHLH (H'D).
1 IC101 0 R/W Clears masking of the
interrupt source of
IRL7 to
IRL4 = HHHL (H'E).
0 — 0 R Reserved
This bit is always read as 0. The write value should
always be 0.