Renesas SH7781 - Manual (Page 893)

19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 863 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Internal
Update Description
4 ABRE 0 R/W None Alpha Blend Ratio Enable
0: The 31 to 24 bits in the color palette registers
1 to 4 and the PnBRSL bits in the plane n
blend ratio registers (PnALPHAR) are
disabled.
The alpha blend ratio is set only by the
PnALPHA bits PnALPHAR.
1: The 31 to 24 bits in the color palette registers
1 to 4 and the PnBRSL bits in PnALPHAR are
enabled.
• The following can be selected as the alpha
blend ratio. Selection is performed using the
PnBRSL bits in PnALPHAR.
• PnALPHA bits in PnALPHAR
⎯ The 31 to 24 bits in the color palette
registers 1 to 4
⎯ Alpha plane data (display data)
For the alpha blend ratio, refer to section 19.4.9,
Superpositioning of Planes.
3 to 1
⎯ All
0 R
⎯ Reserved
These bits are always read as undefined. The
write value should always be 0.
0 DSAE 0 R/W None Display Area Start Address Enable
0: The 28 to 4 bits in the plane n display area
start address 0 and 1 registers (PnDSA0R
and PnDSA1R) are enabled.
The 31 to 29 bits are B'000.
1: The 31 to 4 bits PnDSA0R and PnDSA1R are
enabled.