6 interrupt exception handling and priority – Renesas SH7781 User Manual
Page 359
10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 329 of 1658
REJ09B0261-0100
An interrupt request is masked if priority level H'01 is set.
INTC distinguishes between priority levels H'1A and H'1B,
although both become the same level after truncating the
least significant bit for the CPU.
INTC
Priority level: higher (H'1B) lower (H'1A)
CPU
Priority level: Regarded as the same level (H'D)
If multiple interrupt requests from on-chip modules
occur simultaneously, the INTC processes the interrupt with
the higher priority level (H'1B in the above case).
However, if an external interrupt request is also generated
at the same time the external interrupt request will have
higher priority in the following cases:
- an NMI interrupt request
- an IRQ or IRL interrupt request that has the same or
higher priority level (H'D or greater in the above case).
INTC
Priority level: H'01
CPU
Priority level: H'0 (interrupt is masked)
Priority level H'01 becomes H'00 after the least significant
bit is truncated, so the CPU is not notified of the
corresponding interrupt. The range of priority levels in
the interrupt priority register thus H'02 to H'1F
(30 priority levels).
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
1
Figure 10.4 Priority of On-Chip Peripheral Module Interrupts
10.4.6
Interrupt Exception Handling and Priority
Table 10.13 shows the interrupt source, codes for INTEVT, and the order of interrupt priority.
A unique INTEVT code is allocated to each interrupt source. The start address of the exception
handling routine is the same for all of the interrupt sources. Therefore, the INTEVT value is used
to control branching at the start of the exception handling routine. For instance, the INTEVT
values are used to branch to offsets.
The priority of the on-chip modules is arbitrarily specified by setting values from 31 to 2 in
INT2PRI0 to INT2PRI7. The priority values for the on-chip modules are set to 0 by a reset.
When interrupt sources share the same priority level and are generated simultaneously, they are
handled according to the default priority order given in table 10.13.
Values of INTPRI and INT2PRI0 to INT2PRI7 should only be updated when the BL bit in SR is
set to 1. To prevent erroneous interrupt acceptance, only clear the BL bit to 0 after having read one
of the interrupt priority level-setting registers. This guarantees the necessary timing internally.