18 separation width register (spwr) – Renesas SH7781 User Manual
Page 903
19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 873 of 1658
REJ09B0261-0100
19.3.18
Separation Width Register (SPWR)
The separation width register (SPWR) sets the low-level pulse width of the separation pulse for
the CSYNC signal. The value is retained during power-on reset and manual reset.
R/W:
Internal update:
R/W:
Internal update:
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
Bit:
Initial value:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
O
O
O
O
O
O
O
O
O
O
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
SPW
—
—
—
—
—
—
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
Bit:
Initial value:
Bit Bit
Name
Initial
Value R/W
Internal
Update Description
31 to 10
⎯ All
0
R
⎯ Reserved
These bits are always read as 0. The write value
should always be 0.
9 to 0
SPW
Undefined R/W
Yes
Separation Width
The low-level pulse width of the separation pulse
for the CSYNC signal should be set in dot clock
units.
The value set should be smaller than 1/2 the HC
bits in HCR.
To enable this setting, bit 1 of the CSY bits in
DSMR should be set to 1.