Renesas SH7781 - Manual (Page 677)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 647 of 1658
REJ09B0261-0100
(7) Cache Coherency
The PCIC supports cache coherency function.
When the PCIC functions as a target device, cache coherency is guaranteed on the PCI bus for
accesses from a master device both in host mode and normal mode. When a cacheable area of this
LSI is accessed, PCICSCR0/1 and PCICSAR0/1 should be set.
The following shows the usage notes for this function.
• Up to two conditions can be set for the snoop address. These two conditions are logical ORed
for address comparison.
• When this function is used, a flush/purge request is issued to the CPU before memory
read/write is performed in an access by an address hit. It seriously reduces the PCI bus transfer
speed and CPU performance.
• Do not use the prefetch function when using this function. (Do not set the PFE bit in PCICR to
1.)
• Do not use this function when the CPU is in the sleep state. If a cache hit occurs when the CPU
is in the sleep state, an error occurs on the SuperHyway bus and memory read/write is not
performed. Specify the SNPMD bit (snoop mode) in PCICSCR to 00 (to turn off the snoop
function) before the CPU enters the sleep mode. To keep the coherency before/after the CPU
enters the sleep state, execute cache purge before the sleep instruction is executed.
• When using this function, do not use debugging functions using an emulator. (Do not use this
function when using an emulator).
PCI bus address
Internal bus address Cache snoop address register Compare
Execute read/write
Cache flash/purge
Execute read/write
No hit
Hit
Cache snoop control register
Set
Figure 13.16 Cache Flush/Purge Execution Flow from PCI Bus to SuperHyway Bus