Renesas SH7781 User Manual
Page 470
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11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 440 of 1658
REJ09B0261-0100
D3
D2
Tm1
CLKOUT
A
RD/FRAME
CSn
R/
W
D31 to D0
BS
Tmd1w
Tmd1
Tmd2w
Tmd2
Tmd3
Tmd7
Tmd8w
Tmd8
RDY
DACKn
D1
D7
D8
In this example, DACKn is active-high.
Figure 11.35 MPX Interface Timing 12 (Burst Write Cycle, IW
= 0001,
External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer)
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