Renesas SH7781 - Manual (Page 724)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 694 of 1658
REJ09B0261-0100
• DMARS4
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
Ch9MID Ch9RID Ch8MID Ch8RID
• DMARS5
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
Ch11MID Ch11RID Ch10MID Ch10RID
• DMARS0
Bit Bit Name
Initial
Value R/W Descriptions
15
14
13
12
11
10
C1MID5
C1MID4
C1MID3
C1MID2
C1MID1
C1MID0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Transfer request source module ID5 to ID0 for DMA
channel 1 (MID)
See table 14.3.
9
8
C1RID1
C1RID0
0
0
R/W
R/W
Transfer request source register ID1 and ID0 for DMA
channel 1 (RID)
See table 14.3.
7
6
5
4
3
2
C0MID5
C0MID4
C0MID3
C0MID2
C0MID1
C0MID0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Transfer request source module ID5 to ID0 for DMA
channel 0 (MID)
See table 14.3.
1
0
C0RID1
C0RID0
0
0
R/W
R/W
Transfer request source register ID1 and ID0 for DMA
channel 0 (RID)
See table 14.3.