Renesas SH7781 - Manual (Page 347)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 317 of 1658
REJ09B0261-0100
(3) INT2B2: Detailed Interrupt Sources for the DMAC
Module Bit Name Detailed Source Description
DMAC 31 to 14
⎯ Reserved
These bits are read as 0
and cannot be modified.
13 DMAE1 Channels 6 to 11 DMA
address error interrupt
12 DMINT11 Channel 11 DMA transfer
end or half-end interrupt
11 DMINT10 Channel 10 DMA transfer
end or half-end interrupt
DMAC interrupt sources are
indicated. This register indicates
the DMAC interrupt sources
even if the mask setting for
DMAC is made in the interrupt
mask register.
10 DMINT9 Channel 9 DMA transfer
end or half-end interrupt
9 DMINT8 Channel 8 DMA transfer
end or half-end interrupt
8 DMINT7 Channel 7 DMA transfer
end or half-end interrupt
7 DMINT6 Channel 6 DMA transfer
end or half-end interrupt
6 DMAE0 Channels 0 to 5 DMA
address error interrupt
5 DMINT5 Channel 5 DMA transfer
end or half-end interrupt
4 DMINT4 Channel 4 DMA transfer
end or half-end interrupt
3 DMINT3 Channel 3 DMA transfer
end or half-end interrupt
2 DMINT2 Channel 2 DMA transfer
end or half-end interrupt
1 DMINT1 Channel 1 DMA transfer
end or half-end interrupt
0 DMINT0 Channel 0 DMA transfer
end or half-end interrupt