Renesas SH7781 - Manual (Page 695)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 665 of 1658
REJ09B0261-0100
Section 14 Direct Memory Access Controller (DMAC)
This LSI includes an on-chip direct memory access controller (DMAC). Instead of the CPU, the
DMAC can be used to perform data transfers among external devices equipped with DACK
(transfer request acceptance signal), external memory, on-chip memory, memory-mapped external
devices, and on-chip peripheral modules.
14.1 Features
• Number of channels: Twelve channels (channels 0 to 3 can accept an external request)
• Address space: 4 Gbytes on the architecture (Physical address)
• Transfer data length: Byte, word (2 bytes), longword (4 bytes), 16 bytes, and 32 bytes
• Maximum transfer count: 16,777,216
• Address mode: Dual address mode
• Transfer requests:
Choice of external request (channels 0 to 3), on-chip peripheral module request, or auto-
request
The following modules can issue an on-chip peripheral module request.
⎯ SCIF0 to SCIF5, HAC0, HAC1, HSPI, SIOF, SSI0, SSI1, FLCTL, and MMCIF
• Bus mode:
Choice of cycle steal mode (normal mode or intermittent mode) or burst mode
• Priority: Choice of fixed mode and round-robin mode
• Interrupt request: An interrupt request can be generated to the CPU after half of transfers have
ended, all transfers have ended, or an address error has occurred
• External request detection: Choice of low/high level detection and rising/falling edge detection
of DREQ input
• DMA transfer end notification signal: Active levels for DACK can be specified independently