Intel CONTROLLERS 413808 - Manual (Page 100)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
100 Order Number: 317805-001US
2.7.3.2 Outbound Write Request Uncorrectable Data Errors
2.7.3.2.1 Outbound Writes that are not MSI (Message Signaled Interrupts)
As an initiator, the ATU may encounter this error condition when operating in either the
Conventional or PCI-X modes.
Uncorrectable Data Errors occurring during write operations initiated by the ATU may
record the assertion of PERR# from the target on the PCI Bus. In PCI-X mode, this
includes the assertion of PERR# from the target on the PCI Bus following the split
response termination of a non-posted write request. When an error occurs, the ATUs
continue writing data to the target to clear the OWQ of the current outbound write
transaction. Specifically, the following actions with the given constraints are taken by
the ATU:
• When PERR# is sampled active and the Parity Error Response bit in the ATUCMD is
set, set the Master Parity Error bit in the ATUSR. When the Parity Error Response
bit in the ATUCMD is clear, no action is taken. When the Master Parity Error bit in
the ATUSR is set, additional actions are taken:
— When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear,
set the PCI Master Parity Error bit in the ATUISR. When set, no action.
— When the ATU is operating in the PCI-X mode, the SERR# Enable bit in the
ATUCMD is set, and the Uncorrectable Data Error Recover Enable bit in the
PCIXCMD register is clear, assert SERR# , otherwise no action. When the ATU
asserts SERR#, additional actions are taken:
Set the SERR# Asserted bit in the ATUSR
When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set
the SERR# Asserted bit in the ATUISR. When set, no action.
When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set
the SERR# Detected bit in the ATUISR. When clear, no action
Outbound uncorrectable write data errors, do not result in a master completion. In
addition, when the target terminates the transaction (disconnect), the ATU master
must reinitiate the transaction to clear the data from the OWQ.
2.7.3.2.2 MSI Outbound Writes
As an initiator, the ATU may encounter this error condition when operating in either the
Conventional or PCI-X modes.
Uncorrectable Data Errors occurring during MSI write operations initiated by the ATU
may record the assertion of PERR# from the target on the PCI Bus. When an error
occurs, the ATU completes the transaction normally. Then, the following actions with
the given constraints are taken by the ATU:
• When PERR# is sampled active and the Parity Error Response bit in the ATUCMD is
set, set the Master Parity Error bit in the ATUSR. When the Parity Error Response
bit in the ATUCMD is clear, no action is taken. When the Master Parity Error bit in
the ATUSR is set, additional actions are taken:
— When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear,
set the PCI Master Parity Error bit in the ATUISR. When set, no action.
— When the SERR# Enable bit in the ATUCMD is set, assert SERR# , otherwise no
action. When the ATU asserts SERR#, additional actions are taken:
Set the SERR# Asserted bit in the ATUSR.
When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set
the SERR# Asserted bit in the ATUISR. When set, no action.
When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set
the SERR# Detected bit in the ATUISR. When clear, no action.