Intel CONTROLLERS 413808 - Manual (Page 119)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 119
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.7.10 ATU Error Summary
Table 18 summarizes the ATU error reporting for PCI bus errors and Table 19
summarizes the ATU error reporting for internal bus errors. The tables assume that all
error reporting is enabled through the appropriate command registers (unless
otherwise noted). The ATU Status Register records PCI bus errors. Note that the
SERR# Asserted bit in the Status Register is set only when the SERR# Enable bit in
the Command Register is set. The ATU Interrupt Status Registers record Intel XScale
®
processor interrupt status information.
Table 18. ATU Error Reporting Summary - PCI Interface (Sheet 1 of 5)
Error Condition
(Bus Mode
a
)
Bits Set in
ATU Status Register
(ATUSR
b
)
or
PCI-X Status Register
(PCIXSR
c
)
and/or
ECC Logging Registers
d
(ECCLOG)
Bits Set in
ATU Interrupt Status
Register (ATUISR)
Interrupt Mask Bit in
ATUIMR or ATUCR
PCI Bus Error Response (i.e., signal Target-Abort, signal Master-Abort etc.)
Uncorrectable
Address or
Attribute Error
(All)
In Conventional Mode, ignore (Master-Abort) the transaction, and then signal SERR# . In
PCI-X Mode, claim the transaction and complete as when no error had occurred; and, signal
SERR# upon uncorrectable error detection.
(All) SERR# Asserted - bit 14 SERR# Asserted - bit 10 ATUIMR bit 6
(All) N/A SERR# Detected - bit 4 ATUCR bit 9
(All)
Detected Uncorrectable Address
or Attribute Error - bit 20 of the
PCI Configuration and Status
Register
N/A N/A
(All) Detected Parity Error - bit 15 Detected Parity Error - bit 9 ATUIMR bit 7
(PCI-X2) ECCLOG Updated N/A N/A
Correctable
Address or
Attribute Error
(PCI-X2)
The transaction is completed as when no error had occurred. Then the transaction is
forwarded to the internal bus normally.
(PCI-X2) ECCLOG Updated
Detected Correctable Error - bit
14
ATUIMR bit 11
Outbound Read
Request
Uncorrectable
Data Error (All)
Signal PERR# and SERR# (PCI-X Mode Only).
(All) Master Parity Error - bit 8 Master Parity Error - bit 0 ATUIMR bit 2
(PCI-X) SERR# Asserted - bit 14 SERR# Asserted - bit 10 ATUIMR bit 6
(PCI-X) N/A SERR# Detected - bit 4 ATUCR bit 9
(All) Detected Parity Error - bit 15 Detected Parity Error - bit 9 ATUIMR bit 7
Outbound Write
Request
Uncorrectable
Data Error (All)
Signal SERR# (only for PCI-X or MSI Writes).
(All) Master Parity Error - bit 8 Master Parity Error - bit 0 ATUIMR bit 2
(PCI-X or MSI) SERR# Asserted - bit 14 SERR# Asserted - bit 10 ATUIMR bit 6
(PCI-X or MSI) N/A SERR# Detected - bit 4 ATUCR bit 9
Inbound Read
Completion
Uncorrectable
Data Error
(PCI-X)
None.