Intel CONTROLLERS 413808 - Manual (Page 625)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 625
Interrupt Controller Unit—Intel
®
413808 and 413812
10.7.31 Interrupt Priority Register 6 — IPR6
The Interrupt Priority Register 6 is a 32-bit Coprocessor 6 control register used to
assign a priority level to interrupt sources 111 down to 96. The IPR6 control register is
used to assign one of 4 priority levels to each interrupt source independent of the
INTSTR[3:0] registers:
00
2 —
High Priority
01
2 —
Medium/High Priority
10
2 —
Medium/Low Priority
11
2 —
Low Priority
When interrupt vector generation is enabled and there are multiple requests pending
either in the FINTSRC[3:0] or the IINTSRC[3:0] registers, the highest priority vectors
pending for either FIQ or IRQ are presented in the FINTVEC or IINTVEC respectively.
Note: When multiple interrupts at the same priority level are pending for either FIQ or IRQ,
the vector is selected according to a fixed priority based on bit location. Highest order
bit is first.
Table 413. Interrupt Priority Register 6 — IPR6
Bit Default Description
31:30 00
2
MU MSI-X Table Write Interrupt Priority.
29:28 00
2
ATUE Interrupt Message D Priority.
27:26 00
2
ATUE Interrupt Message C Priority.
25:24 00
2
ATUE Interrupt Message B Priority.
23:22 00
2
ATUE Interrupt Message A Priority.
21:10 00
2
Reserved.
09:08 00
2
IMU Interrupt Priority.
07:06 00
2
ATU-E Error Interrupt Priority.
05:04 00
2
ATU-E Configuration Register Write Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL3
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL3
03:02 00
2
ATU-E/Start BIST Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL3
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL3
01:00 00
2
I 2 C Bus Interface 2 Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL3
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL3
Memory
Coprocessor
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Coprocessor address
CP6, Page 8, Register 6