Intel CONTROLLERS 413808 - Manual (Page 520)

Intel
®
413808 and 413812—SRAM Memory Controller
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
520 Order Number: 317805-001US
8.3.3.1 ECC Generation
For write operations, the SMCU generates the error correction code which is written
along with the data. This section describes the operation of the SRAM Control Block for
ECC generation on 32-bit data of the 256-bit wide memory. The SMCU will generate
7-bit wide ECC on every 32-bit data. The algorithm for a write transaction is:
if data to write is 32-bit wide
Generate the ECC_with the G-matrix
Write the new data and ECC
else {Partial Write}
Read entire 32-bit data word from memory
Merge the new data portion with the data from memory
Generate the new ECC with the G-matrix
Write new data and ECC
Figure 57 shows how the data logically flows through the ECC hardware for a write
transaction.
The G-Matrix in Figure 57 generates the ECC. The data to be written is input to the
matrix and the output is the ECC code. Each row of the G-Matrix indicates which data
bits’ codes of DQ[31:0] , DQ[63:32] , DQ[95:64] , or DQ[255:224] needs to be
XORed together to form the ECC code. The resulting ECC bits are driven on
SCB0[6:0]
,
SCB1[6:0]
,
SCB2[6:0]
,
and SCB7[6:0] respectively.
Figure 57. ECC Write Flow
ECC
Memory
D[255:224]
Caculate
ECC
256-bit
Data Path
ECC Memory D[31:0]
MCU
SRAM Memory Array
Caculate
ECC
B6358-01