Intel CONTROLLERS 413808 - Manual (Page 445)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 445
SRAM DMA Unit (SDMA)—Intel
®
413808 and 413812
5.3.1 Interrupt Control for SDMA
Refer to the silicon C Spec for full register definitions, the following control the SDMA:
INTPND2:
bit 13: SDMA Error Interrupt Pending
bit 12: SDMA Normal Interrupt Pending
INTCTL2:
bit 13: SDMA Error Interrupt Mask.
0 = Masked
1 = Not Masked
bit 12: SDMA Normal Interrupt Mask.
0 = Masked
1 = Not Masked
INTSTR2
bit 13: SDMA Error Interrupt Steering.
0 = Interrupt Directed to internal IRQ
1 = Interrupt Directed to internal FIQ
bit 12: SDMA Normal Interrupt Steering.
0 = Interrupt Directed to internal IRQ
1 = Interrupt Directed to internal FIQ
INTSRC2
bit 13: SDMA Error Interrupt
0 = Not Interrupting or Not steered to internal IRQ exception or masked by
INTCTL2
1 = Interrupting and steered to internal IRQ exception and unmasked by
INTCTL2
bit 12: SDMA Normal Interrupt
0 = Not Interrupting or Not steered to internal IRQ exception or masked by
INTCTL2
1 = Interrupting and steered to internal IRQ exception and unmasked by
INTCTL2
FINTSRC2
bit 13: SDMA Error Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by
INTCTL2
1 = Interrupting and steered to internal FIQ exception and unmasked by
INTCTL2
bit 12: SDMA Normal Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by
INTCTL2
1 = Interrupting and steered to internal FIQ exception and unmasked by
INTCTL2
IPR
27:26: SDMA Error Interrupt Priority
25:24: SDMA Normal Interrupt Priority