Intel CONTROLLERS 413808 - Manual (Page 338)

Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
338 Order Number: 317805-001US
3.17.52 ATU Power Management Capabilities Register - APMCR
Power Management Capabilities bits adhere to the definitions in the PCI Bus Power
Management Interface Specification, Revision 1.1. This register is a 16-bit read-only
register which provides information on the capabilities of the ATU function related to
power management.
Table 192. ATU Power Management Capabilities Register - APMCR
Bit Default Description
15:11 00000
2
PME_Support - Not capable of asserting the PME# signal in any state, since PME# is not supported by
the 4138xx.
10 0
2
D2_Support - Set to 0
2
indicating the 4138xx does not support the D2 Power Management State
9 1
2
D1_Support - Set to 1
2
indicating that the 4138xx supports the D1 Power Management State
8:6 000
2
Aux_Current - This field is set to 000
2
indicating that the 4138xx has no current requirements for the
3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1
5 0
2
DSI - Set to 0
2
meaning that this function does not require a device specific initialization sequence
following the transition to the D0 uninitialized state.
4 0
2
Preserved.
3 0
2
PME Clock - Does not apply to PCI Express.
Hard-wired 0
2:0 010
2
Version - Setting these bits to 010
2
means that this function complies with PCI Bus Power Management
Interface Specification, Revision 1.1
PCI
IOP
Attributes
Attributes
15 12 8 4 0
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
pr
pr
ro
ro
ro
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+09AH